Workshop on Fast design of digital systems

The Spain Chapter of the IEEE Circuits and Systems organized  a  Workshop on Fast Design of Digital Systems, which was locally organized by the "Universidad San Pablo CEU" in Madrid, Spain on March 8 and  9, 2018. The workshop was held at Escuela Politécnica Superior, University San Pablo CEU in Madrid.  It was aimed at researchers and hardware engineers and it covered the  fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high‐level programming language and the output is fully functional VHDL.

 

The workshop was given by Prof. Madhav P. Desai, from the Indian Institute of Technology, Bombay. The first day was devoted to an introduction to the design tool AHIR, and the second day was a lab session. Attendants were engineers, researchers and undergrad students coming from the Spanish Aerospace Institute (INTA), University CEU San Pablo and Universidad Politécnica de Madrid. The attendants were able to develop and debug several algorithms using C as the entry language and obtaining automatically the synthesizable VHDL code.

 

 

TECHNICAL PROGRAM

 

MARCH 8

 

8:30 – 12:30:     Theoretical session

 

  •  Introduction to the AHIR tool suite
  • Language Aa
  • VHDL generation
  • Verification              

 

MARCH 9

 

8:30 – 12:30:    Lab  session

 

  •  Case study: real‐time ECG characterization

 

BIOGRAPHY OF THE SPEAKER

 

Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay and a PhD degree from University of Illinois in Urbana‐Champaign. During the period 1992‐1996 he was with the Semiconductor Engineering Group of Digital Equipment Corporation in Hudson, MA, where he worked as Principal Engineer developing two of the fastest CMOS microprocessors in history. Currently, he is a Full Professor at the Department of Electrical Engineering, Indian Institute of Technology, Bombay. His research lines cover VLSI design, circuits and systems, and combinatorial algorithms.

 

More details can be found at https://events.vtools.ieee.org/m/168394

 

 

 

 

HIGHLIGHTS

  • IEEE CASS Distinguished Lecturer Sudipto Chakraborty, "Ultra-low Power Cryo-CMOS Designs for Next-Generation Quantum Computing", 2023, Malaga. Details  here
  • Electronics Week   at Public University of Navarra, Pamplona, on February  6-8, 2023. See more details  here.
  • Seasonal School: Efficient Circuits and Systems for Brain-Inspired Computing (Link)
  • Electronics Week   at Public University of Navarra, Pamplona, on February 6-8, 2023. See more details  here.
  • Workshop on professional perspectives of PhD graduates​ within the WASC Workshop [Link]
  • Electronics Week   at Public University of Navarra, Pamplona, on January 31 - February 2, 2022. See more details  here.
  • New LinkedIn profile. Follow us! [Link]
  • Elections of new Chapter Officers, 2021. See more details [Link]
  • 2021 Chapter Anual Meeting at DCIS. See more details [Link]
  • Webinar on MEMS Technologies and Applications, Oct.  25 2021. See more details [Link]
  • IEEE Spain celebrates IEEE Day, on October 22-23, 2021. See more details [Link]
  • Electronics Week   at Public University of Navarra, Pamplona, on February  2-5, 2021. See more details  here.
  • Chapter annual meeting held virtual on November 19th at DCIS 2020. See more details here.
  • Keynote talk by DLP Vivek De at DCIS 2020, on November 18th, 2020. See more details here.
  • Spain CASS Chapter promotes Panel YP at ISCAS 2020 among PhD students, open to everyone. See more detais here.
  • IEEE Spain celebrates IEEE Day, on October, 21-23, 2020. See more details here.
  • Technical meeting at ISCAS 2020 (virtual networking session) on October 19, 2020. See more details here.
  • Electronics Week   at Public University of Navarra, Pamplona, on February  4-6, 2020. See more details  here.