The Spain Chapter of the IEEE Circuits and Systems Society co-organized for the second year in a row the Workshop on Fast Design of Digital Systems, which was locally organized by the University San Pablo CEU in Madrid, Spain on February 20-21, 2019. The workshop was held at Escuela Politécnica Superior, University San Pablo CEU. It was a two-day event aimed at researchers and hardware engineers and covering the fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high-level programming language and the output is fully functional VHDL. All sessions were composed of theory and practice. Examples were tested on FPGA boards. In day 1 there was an overview on the latest FPGA trends provided by Ricardo Gómez Galarza, from AVNET-Silica.
Attendants were researchers, professors and undergraduate students from University San Pablo CEU, University of Málaga and University of Extremadura.
10:00-10:15 h: Welcome message (Gabriel Caffarena, USP-CEU)
10:15-11:00 h: New trends in FPGA and configurable Soc design (Ricardo Gómez Galarza, AVNET-Silica)
11:00-11:15 h: Coffee break
11:15-13:30h: Lab session I: Introduction to AHIR toolchain (Madhav P. Desai, IIT-Bombay)
9:30-11:00h: Lab session II: More on AHIR toolchain (Madhav P. Desai, IIT-Bombay)
11:00-11:15h: Coffee break
11:15-13:30h: Lab session III: Signal processing case study (Madhav P. Desai, IIT-Bombay)
BIOGRAPHY OF THE SPEAKERS
Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay and a PhD degree from University of Illinois in Urbana-Champaign. During the period 1992-1996 he was with the Semiconductor Engineering Group of Digital Equipment Corporation in Hudson, MA, where he worked as Principal Engineer developing two of the fastest CMOS microprocessors in history. Currently, he is a Full Professor at the Department of Electrical Engineering, IIT Bombay. His research covers VLSI design, circuits and systems, and combinatorial algorithms.
Gabriel Caffarena is an Associate Professor at University CEU-San Pablo. His research focuses on Hardware acceleration of Signal Processing algorithms.
More details can be found at https://events.vtools.ieee.org/m/189107